Position Description:
The key responsibility for the position is to debug andbring up the ATE testprogram and release to mass production, including testplan definition, ATE related HW design, ATE program debugging and productionramp up.

The position requires the candidate working closely with SOCdesign/verification/validation and OSATs.

主要工作职责为开发ATE测试程序并release到封测厂进行量产， 包括测试方案撰写，ATE相关硬件设计，ATE程序开发和debug， 量产导入等。

本职位要求ATE测试工程师能与SOC设计，验证人员以及外包供应商（OSAT以及其他相关测试服务供应商等）协同工作进行开发。

Required Skills:
3+ years working experience as ATE Engineer
Solid knowledge of ATE Testmethodologies and ProgramDevelopment

Capability of IP level testplan development, especially analog IP andphy IP related testplan development.

Experience on major ATE platforms such as Advantest V93k, TeradyneUltra Flex, J750, etc.

Capability of ATE related HW(Loadboard/socket/probecard) design &review

Well management with outsourcing vendors

Strong problem-solving skill and good schedule keeper
Good team player

3年以上ATE 工作经历

深入理解ATE测试原理及程序开发

具备独立撰写testplan的能力，尤其是analog IP及phy IP的testplan

具有主要ATE平台的开发经历，如爱德万V93k， 泰瑞达 Ultra Flex, J750等

具有ATE相关硬件（Loadboard/socket/probecard）的设计和review经验

具有良好的供应商管理能力，团队协作能力，问题解决能力，按期交付能力

Education Requirement:
- B.Sc and above degree from China top universitieswith major on EE, Micro Electronic,
Information Engineering, Telecommunication, orAutomation etc

毕业于电子，微电子，信息科学等相关专业

Job Description:

As part of the ASIC design team, engineer will mainly focus on following areas, but not limited to:

1、Block, IP and SoC level DFT implementation including: RTL coding integration, Mbist insertion/simulation, Scan insertion & compression, Lbist insertion & simulaton, on chip clocking for at-speed test, boundary scan, analog/hard IP test.

2、Block level dft drc check & fix it in RTL/Netlist level.

3、Block level DFT constraint generation, synthesis, STA, ECO and formal check.

4、Test patterns/vectors generation and verification, Fault coverage data collection and improve.

Job Description:

As part of the ASIC design team, engineer will mainly focus on following areas, but not limited to:

1、Block, IP and SoC level DFT implementation including: RTL coding integration, Mbist insertion/simulation, Scan insertion & compression, Lbist insertion & simulaton, on chip clocking for at-speed test, boundary scan, analog/hard IP test.

2、Block level dft drc check & fix it in RTL/Netlist level.

3、Block level DFT constraint generation, synthesis, STA, ECO and formal check.

4、Test patterns/vectors generation and verification, Fault coverage data collection and improve.

Job Description:

As part of the ASIC design team, engineer will mainly focus on following areas, but not limited to:

1、Block, IP and SoC level DFT implementation including: RTL coding integration, Mbist insertion/simulation, Scan insertion & compression, Lbist insertion & simulaton, on chip clocking for at-speed test, boundary scan, analog/hard IP test.

2、Block level dft drc check & fix it in RTL/Netlist level.

3、Block level DFT constraint generation, synthesis, STA, ECO and formal check.

4、Test patterns/vectors generation and verification, Fault coverage data collection and improve.

Job Description:

As part of the ESL architecture team, engineer will mainly focus on following areas, but not limited to:

1、Architecture exploring for the complex SoC and high-speed subsystem include but not limited to memory, interconnection, ISP, GPU, CPU, and etc.

2、Bring up the virtual platform and analysis the performance and power simulation result.

3、Write the high quality SystemC/C++/TLM2 model for the memory, interconnection, and other high-speed subsystem.

4、Work out the highly configurable work load model for the various components in various scenarios.

5、Work out the SoC use case and performance goal in system level with help from product engineer.

6、Assist design engineer to work out the ASIC micro-architecture.

7、Co-work with verification engineer, design engineer, and software engineer to qualify and improve the quality of models.

Job Description:

As part of the ESL architecture team, engineer will mainly focus on following areas, but not limited to:

1、Architecture exploring for the complex SoC and high-speed subsystem include but not limited to memory, interconnection, ISP, GPU, CPU, and etc.

2、Bring up the virtual platform and analysis the performance and power simulation result.

3、Write the high quality SystemC/C++/TLM2 model for the memory, interconnection, and other high-speed subsystem.

4、Work out the highly configurable work load model for the various components in various scenarios.

5、Work out the SoC use case and performance goal in system level with help from product engineer.

6、Assist design engineer to work out the ASIC micro-architecture.

7、Co-work with verification engineer, design engineer, and software engineer to qualify and improve the quality of models.

Job Description:

As part of the ESL architecture team, engineer will mainly focus on following areas, but not limited to:

1、Architecture exploring for the complex SoC and high-speed subsystem include but not limited to memory, interconnection, ISP, GPU, CPU, and etc.

2、Bring up the virtual platform and analysis the performance and power simulation result.

3、Write the high quality SystemC/C++/TLM2 model for the memory, interconnection, and other high-speed subsystem.

4、Work out the highly configurable work load model for the various components in various scenarios.

5、Work out the SoC use case and performance goal in system level with help from product engineer.

6、Assist design engineer to work out the ASIC micro-architecture.

7、Co-work with verification engineer, design engineer, and software engineer to qualify and improve the quality of models.

Job Description:

1、Work with an experienced design team to design analog block for automotive SOC or MCU.

2、Responsible for analog design, simulation, layout supervision, tape out and silicon verification.

3、Work closely with design validation and characterization team to support successful product release.

4、Experience on GPIO, ADC, DAC, Regulator(DCDC or LDO) design skill is a plus.

5、Candidates must be self-motivated, driven and hard workin.

Job Description:

1、Work with an experienced design team to design analog block for automotive SOC or MCU.

2、Responsible for analog design, simulation, layout supervision, tape out and silicon verification.

3、Work closely with design validation and characterization team to support successful product release.

4、Experience on GPIO, ADC, DAC, Regulator(DCDC or LDO) design skill is a plus.

5、Candidates must be self-motivated, driven and hard workin.